Programmable integrated circuits (ICs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of programmable IC, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of programmable IC is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For these exemplary programmable ICs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
A circuit design for a programmable IC is typically initially described in the form of an HDL (hardware description language) behavioral description (e.g., VHDL or Verilog code). The circuit description is compiled into a netlist, a description of elements included in the circuit and the interconnections among the elements, using a synthesis tool. The synthesis tool converts the HDL description into a circuit implementation that incorporates specific elements selected from a library of available elements. When the library elements correspond to the elements available in a programmable IC, the synthesis output is a netlist appropriate for implementation in that programmable IC.
In other instances, the netlist may be generated from a schematic, where the schematic is implemented using icons corresponding to the same library elements.
In either case, the netlist is then provided to implementation software, which “maps” the elements of the circuit to elements physically present in the programmable IC, “places” the mapped elements into specific instances of the available elements, and “routes” signal paths among the various placed elements as dictated by the netlist. The mapped, placed, and routed design is then converted into a stream of bits (the configuration data) that can be used to program the design into a programmable IC.
The placement and routing phases are often accomplished as a single step, because while the routing naturally depends upon the placement, the placement may also benefit by taking into consideration the number and type of available routing resources between the programmable elements in various locations. Thus, this set of implementation tools is often referred to as “place-and-route software”.
Place-and-route software can benefit from the provision of “constraints”, e.g., a constraints file that indicates certain circuit requirements, such as maximum delays on various paths, or a maximum clock frequency in a synchronous design. Another type of constraint that is sometimes used for synchronous designs is a listing of “multi-cycle paths”. A multi-cycle path is any path in the design that originates at the output of one synchronous element (a clocked element such as a flip-flop, for example) and extends to the input of another synchronous element that does not change state more often than every N clock cycles, where N>=2. In other words, the destination element changes state no more often than every other clock cycle.
Clearly, it can be beneficial to indicate multi-cycle paths, to prevent the place-and-route software from consuming unnecessary resources by attempting to route a multi-cycle path within the time period of a single clock cycle. However, many users are unaware of the desirability of such constraints. Further, some users may be unaware of the presence of multi-cycle paths in their designs, particularly when the circuit is specified using a high-level design tool or HDL. Therefore, it is not uncommon for place-and-route tools to attempt to impose single-cycle timing on multi-cycle paths within a circuit, to the overall detriment of circuit performance. In some instances, place-and-route software may even report failure to implement the design within the specified timing constraints, when in reality the design does meet the timing criteria for the design.
Therefore, it is desirable to provide methods by which multi-cycle paths can be taken into consideration during the place-and-route process, without requiring manual intervention to identify the multi-cycle paths.